Так, Сергій Єгоров абсолютно правий:
Models for Socket 754
Paris (130 nm SOI)
L1-Cache: 64 + 64 KiB (Data + Instructions)
L2-Cache: 256 KiB, fullspeed
MMX, 3DNow!, SSE, SSE2
Enhanced Virus Protection (NX bit)
Integrated 72-bit(
Single channel, ECC capable) DDR memory controller
Socket 754, 800 MHz HyperTransport
VCore: 1.4 V
First release: July 28, 2004
Clockrate: 1800 MHz (3100+)
Stepping: CG (Part No.: *AX)
Palermo (90 nm SOI)
Early models (stepping D0) are downlabeled "Oakville" mobile Athlon64
L1-Cache: 64 + 64 KiB (Data + Instructions)
L2-Cache: 128/256 KiB, fullspeed
MMX, 3DNow!, SSE, SSE2
SSE3 support on E3 and E6 steppings
AMD64 on E6 stepping
Cool'n'Quiet (Sempron 3000+ and higher)
Enhanced Virus Protection (NX bit)
Integrated 72-bit(
Single channel, ECC capable) DDR memory controller
Socket 754, 800 MHz HyperTransport
VCore: 1.4 V
First release: February 2005
Clockrate: 1400 - 2000 MHz
128 KiB L2-Cache (Sempron 2600+, 3000+, 3300+)
256 KiB L2-Cache (Sempron 2500+, 2800+, 3100+, 3400+)
Steppings: D0 (Part No.: *BA), E3 (Part No.: *BO), E6 (Part No.: *BX)
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